1. Field of the Invention
The present invention relates to a receiver for a memory controller and the method thereof, particularly to a receiver for a memory controller, which substitutes a memory's data strobe signal for a self-generated emulated data strobe signal to avoid malfunction caused by noise resulting from transmission of the data strobe signal.
2. Description of the Prior Art
Dominated mainly by the data transfer rate, performance of SDRAM doubly increases when Single Data Rate (SDR) migrates to Double Data Rate (DDR) SDRAM, in which data are transferred on both edges of the SDRAM clock. Accompanied with the data transferred in DDR SDRAM systems, a data strobe signal is also transmitted for synchronization.
FIG. 1 is a diagram showing a conventional receiver for a memory controller. The receiver 1 comprises a push pointer strobe signal generator 101 composed of a Schmitt trigger 11 and delay circuit 13a, a data strobe signal delay circuit 102 composed of a one-ended differential buffer 12 and delay circuit 13b, a first and second push pointer generator 14a and 14b, buffers 15a and 15b, and data collector 16. The push pointer strobe signal generator 101 outputs a signal Push-PTR DQS to the first and second push pointer generator 14a and 14b. The data strobe signal delay circuit 102 outputs a delayed data strobe signal Delayed DQS to the buffers 15a and 15b. 
The operation of the conventional receiver 1 will be explained in the following. A memory (not shown) sends data and a data strobe signal READ_DQS to the memory controller when the memory controller sends a data request signal to request the data from the memory. The push pointer strobe signal generator 101 and the data strobe signal delay circuit 102 of the receiver 1 receive the data strobe signal READ_DQS from the memory and generate signals Push-PTR DQS and Delayed DQS. The push pointer generator 14a and 14b generate push pointers PTR1 and PTR2 having priorities, receive and respond to the signal Push-PTR DQS by outputting to the buffers 15a and 15b the push pointers PTR1 and PTR2 in an order according to the priorities upon the rising and falling edges of the signal Push-PTR DQS. The buffers 15a and 15b receive and respond to the signal Delayed DQS and the push pointers PTR1 and PTR2 by alternatively storing the data in memory addresses corresponding to the push pointers PTR1 and PTR2 upon rising and falling edges of the signal Delayed DQS. The data collector 16 collects the data stored in the buffers 15a and 15b. 
However, in the previously described receiver, noise in the data strobe signal READ_DQS resulting from the transmission between the memory and the controller easily causes malfunction of the receiver. FIG. 2 is a diagram showing the waveforms of the signals Push-PTR DQS, Data and PTR1. The noisy signal READ_DQS results in noise in the signal Push-PTR DQS. An unintended rising edge appears in the signal Push-PTR DQS and causes wrong push pointer PTR1 and PTR2 from the push pointer generators 14a and 14b when the noise is too large. This results in wrong storage od the data in the buffers 15a and 15b. 